1. Field of the Invention
This invention relates to a serially-accessed type semiconductor memory device, and more particularly, to a semiconductor memory device of the type where, during the time a given address is being serially accessed, a serial access operation can be performed in relation to another address.
2. Description of the Related Art
Serially-accessed type memory devices have been developed which can operate at a high speed. In the memory devices, two data selecting/fetching systems are provided in a single semiconductor chip. When one of the data selecting/fetching systems is outputting data, the other is setting up other data to be output. This type of memory device is also referred to as an interleave type memory device.
FIG. 1 illustrates, in block form, a major part of an interleave type semiconductor memory device which was invented by the author(s) of the present patent application and filed July 25, 1987, bearing U.S. application Ser No. 066,260. In this figure, a system A as one of the two selecting/fetching systems contains data registers 51.sub.1, 51.sub.2, . . . A system B as the other of those two data selecting/fetching systems contains data registers 52.sub.1, 52.sub.2, bit data as previously stored in a memory array (not shown).
Column select gates 53.sub.1, 53.sub.2, . . . select the data in data register 51 of system A, according to the signals on column select lines CA0, CA1, . . . of system A. Similarly, column select gates 54.sub.1, 54.sub.2, . . . select data in data register 52 of system B, according to the signals on column select lines CB0, CB1, . . . of system B. Data buses DBA and DBA, incorporated in system A, are supplied with the data selected by column select gate 53, also incorporated in system A. Likewise, data buses DBB and DBB, incorporated in system B, are supplied with the data selected by column select gate 54, which is incorporated in system B. A drive signal generator 56 supplies a drive signal to address generator 55. Reference numeral 57 designates a serial address generator in the system B. A drive signal generator 58 in the system B supplies a drive signal to address generator 57. Address decoders 59.sub.1, 59.sub.2, . . . in the system A are supplied with an output address from serial address generator 55. Address decoders 61.sub.1, 61.sub.2, . . . in the system B is supplied with the output address from serial address generator 57. Column select gate drivers 61.sub.1, 61.sub.2, . . . of the system A are supplied with a decoder output of address decoder 59. Column select gate drivers in the system B 62.sub.1, 62.sub.2, . . . are supplied with the decoder output of address decoders 60, respectively. Data bus select gate 63 selects a data of data bus DBA or DBA. Data bus select gate 64 selects a data of data bus DBB or DBB. Output driver 65 outputs data OUT.
Drive signal generators 56 and 58 of the systems A and B generate drive signals input to serial address generators 55 and 57, and other drive signals for controlling other circuits of these systems. The other drive signals contains signals to selectively activate column select gates 53 and 54, and data bus select gates 63 and 64. The drive signals generated by those signals generators are not illustrated, for simplicity.
The conventional semiconductor memory shown in FIG. 1 operates as illustrated by timing charts shown in FIGS. 2A to 2D. In this instance, the data access, or the data outputting from the data registers is performed in the order of data registers 51.sub.1, 51.sub.2, . . . . A serial access to be described is for the case of a cycle time to access the data of data register 51 contained in the system A. Specifically, since the preceding cycle is the cycle to access the system B, data bus select gate 63 in the system A is inactive, or in an off state as in step S1 of FIG. 2B. Data bus select gate 64 in the system B is active, or in an on state, as in step S16 of FIG. 2C. In the system B, as shown in the subsequent steps S17 and S18, the data of the data register in the system B, e.g., the data of data register 52.sub.1, is transferred to output driver 65, via data buses DBB and DBB.
In the system A, which is disconnected from output driver 65 in the preceding cycle, an address is set by serial address generator 55, according to the drive signal output from drive signal generator 56 (step S2), address decoder 59 of the system A is selected (S3), and the decoder output renders column select line CA1 active (step S4), and the data of data register 51.sub.2 is transferred to data buses DBA and DBA, as shown in step S5.
When the serial access enters the present cycle, data bus select gate 64 of the system B is made inactive as shown in step S11, and the data bus select gate 63 of the system A is made active as shown in step S6. As a result, the data buses DBA and DBA in the system A are connected to output driver 65, so that the data from data register 51.sub.2 is transferred to output driver 65, as shown in step S8. Then, it is output from output driver 65. At this time, in the system B which is disconnected from output driver 65, an address is set by serial address generator 57 according to the drive signal, which is output from drive signal generator 58 during the period from step S11 to S15, to select address decoder 60 in the system B. Further, column select line CB1 is made active by the decoder output. As a result, the data in data register 52.sub.2 is transferred to data buses DBB and DBB bar, thereby completing the set-up for access in the next cycle.
As seen from the foregoing description, the memory device of the interleave type substantially halves the cycle time when comparing with the memory device of other access system, and the access time is remarkably improved.
In the memory device of the interleave type, the circuits in the systems A and B operate at the period, which is twice the period of an external serial access control signal (FIG. 2A) applied to drive signal generators 56 and 58, and these circuits operate with half-period staggered phase. To cause serial address generators 55 and 57 of the systems A and B to set addresses, drive signals with different phases must be generated by drive signal generators 56 and 58. It is assumed now that a serial access control signal applied to drive signal generators 56 and 58 is SC, and that the drive signals of the two systems which are generated by these drive signal generators 56 and 58 and vary at the double period of the period of signal SC, are designated by .phi.X and .phi.Y, respectively. These drive signals .phi.X and .phi.Y vary like the least significant bit signal of the address for serial access. As a matter of course, the serial address generator 55 of the system A is constantly supplied with drive signal .phi.X as generated by the drive signal generator 56 in the system A. Likewise, the serial address generator 57 of the system B is constantly supplied with drive signal .phi.Y as generated by the drive signal generator 58 in the system B.
The above serial access system in which the drive signal .phi.X of the system A is supplied to the circuits of the system A and the drive signal .phi.Y of the system B is supplied to the circuits of the system B, involve the following problems. At the start of or during the serial access, if a start address of the serial access must be designated, one of the systems A and B must be started earlier than the other according to the least significant bit (LSB) of the serial access at that time. In the conventional serial access system of the memory device, however, the systems A and B alternately operate according to serial access control signal SC, and it is impossible to start the system A or B in a desired operation cycle. For this reason, the conventional memory device cannot execute various applied operations of the serial access, such as designation of the serial start address, and jump during the serial access.
As described above, in the conventional serially-accessed semiconductor memory device which uses the two data selecting/fetching systems and alternately operates them for data fetching, it is impossible to start a desired one of those two systems earlier than the other in a desired operation cycle. Therefore, the conventional memory device cannot execute the various applied operations of the serial access.